The present invention relates to a video random access memory (video RAM) used as a dual port memory. More particularly, the present invention relates to the video RAM which suppresses peak current during data transfer operations performed between a random access memory and a serial access memory. The present invention further relates to a method for suppressing the peak current in a serial access memory block.
Recently, with the rapid spread of portable computers such as notebook computers, video RAM technology has become an important and evolving field. A video RAM used as a dual port memory functions as both a dynamic random access memory (DRAM) and as serial access memory (SAM). The typical video RAM has a DRAM port connected to a CPU in the overall computer system, and the SAM port connected to a peripherial device, such as a cathode ray tube (CRT), a liquid crystal diplay (LCD), or a video camera. The SAM port and RAM port operate independently, but may cooperate to transfer data.
SAMs have a wide variety of applications for various systems. SAMs are characterized by asynchronous operation, and very high data transfer speeds. Conventional video RAMs may contain either a full SAM or a half SAM. For example, the NEC video RAM identified as .mu.PD482445 employs a full SAM, while the Texas Instruments video RAM identified as TMS55160 employs a half SAM. However, in either configuration, the increasing variety of operational functions required of video RAMs require video RAMs having higher data storage capacity. This requirement necessitates increased integration density in video RAMs.
FIG. 1 is illustrative of the conventional video RAM. Further details of the conventional video RAM can be obtained from published technical articles such as the 1985 ISSCC paper "A 256K Dual Port Memory." In FIG. 1, the construction and operation of the RAM port are the same as those used in conventional DRAMs. As shown, a plurality of sense amplifiers 4 amplify data signals to and from a memory cell array 6. A dotted line block 10 indicates a SAM block, often referred to as a data register block, having a plurality of latch circuits. Each latch circuit comprises two inverters having input and output terminals oppositely connected to bit lines BL and BL/. Data transfer gates consisting of NMOS transistors T1, T2, . . . , Tn are formed on the bit lines BL and BL/ and connect SAM block 10 with memory cell array 6. Each data transfer gate receives a data transfer gate enable signal DTP.
In the illustrative video RAM, the SAM block is typically 512.times.4, 512K.times.8, or 512K.times.16, etc. The 512K.times.4 size SAM is usually associated with a 1M video RAM, where M=2.sup.20, the 512K.times.8 size SAM with a 2M video RAM, and the 512.times.16 size SAM with the 4M video RAM. Operation of the SAM block via the SAM port is typically performed after data is transferred through data transfer gates T1, T2, . . . , Tn. That is, SAM block 10, whether having a 512K.times.4, 512K.times.8, or 512K.times.16 size, is enabled all at once. Thereafter, data is transferred.
Increasing block size correspondingly increases the amount of data transferred. At contemporary block sizes and given the corresponding quantity of data transferred, a problem has arisen in the level of peak current through the power and ground voltage terminals of the latch circuits of SAM block 10. Since the level of peak current generated is proportional to the density of the semiconductor memory device, the problem will only become more serious as memory device densities continue to increase.
Increased peak current brings with it increased noise on the the ground and power terminals of the the latch circuits. This increased noise level destabilizes the logic threshold voltage VT of transistors in the memory device, thus leading to device malfunction. The noise generated by increased peak current can additionally cause the operating voltage potential for data transferred to the SAM block to reversed from a defined potential, thereby reducing reliability in the video RAM.